gcc - Export preprocessor macro in makefile -


i want export preprocessor macro internal makefile main makefile in particular target.

example: main_makefile

target1 :    cxxflags+=-dnewflag=newflag    cd some_directory; make

here want use value of cxxflags -dnewflag=newflag , defined under target1 in some_directory/make

please let me know how can achieve this.

there no way append variable command line, unless you've made arrangements in makefile of subdirectory.

the simplest thing use different variable, this:

target1:         cd some_directory && $(make) extra_cxxflags=-dnewflag=newflag

(note should always use $(make) or ${make} when invoking sub-make, never make directly.)

then in subdirectory makefile this:

cxxflags += $(extra_cxxflags)

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