fpga - How can write code in verilog shorter using case sentence -


i new in verilog , still have problems basics. following code 1 of modules , works way want, wonder if can written more efficient , shorter , how done. thank help!

`timescale 1ns / 1ps   module counter   (     input a_i,     input b_i,     input enable_i,     input clk,     input reset,     input r_i,     input up_down_i, // za realno stanje se up_down_o prepisuje v up_down_i     output reg signed [7:0] value_o,     output reg up_down_o     );      reg a;   reg b;   reg signed [7:0] value_cmp;   wire [1:0] a_b={a,b};    initial value_o = 8'b00000000;   initial value_cmp = 8'b00000000;   initial = 1'b0;   initial b = 1'b0;   initial up_down_o = 1'b1;     always@ (posedge clk or posedge reset)   begin     <= a_i;     b <= b_i;     value_cmp <= value_o;       if (reset || r_i)     begin       value_o<= 8'b0;       value_cmp <=8'b0;       end      else if (enable_i)     begin  //up or down       if (up_down_i)       begin  //up         if ((a == 1'b0) && (a_i == 1'b0) && (b == 1'b0) && (b_i == 1'b1))           value_o <= value_o+1;           else if ((a == 1'b0) && (a_i == 1'b1) && (b == 1'b1) && (b_i == 1'b1))           value_o <= value_o+1;           else if ((a == 1'b1) && (a_i == 1'b1) && (b == 1'b1) && (b_i == 1'b0))           value_o <= value_o+1;           else if ((a == 1'b1) && (a_i == 1'b0) && (b == 1'b0) && (b_i == 1'b0))           value_o <= value_o+1; // change         if ((a == 1'b0) && (a_i == 1'b1) && (b == 1'b0) && (b_i == 1'b0))             value_o <= value_o+1;         else if ((a == 1'b1) && (a_i == 1'b1) && (b == 1'b0) && (b_i == 1'b1))             value_o <= value_o+1;           else if ((a == 1'b1) && (a_i == 1'b0) && (b == 1'b1) && (b_i == 1'b1))             value_o <= value_o+1;         else if ((a == 1'b0) && (a_i == 1'b0) && (b == 1'b1) && (b_i == 1'b0))             value_o <= value_o+1; // after           else if (a == a_i ==b == b_i )             value_o <= value_o+1;                     end        else       begin  //down           if ((a == 1'b0) && (a_i == 1'b1) && (b == 1'b0) && (b_i == 1'b0))             value_o <= value_o-1;         else if ((a == 1'b1) && (a_i == 1'b1) && (b == 1'b0) && (b_i == 1'b1))             value_o <= value_o-1;           else if ((a == 1'b1) && (a_i == 1'b0) && (b == 1'b1) && (b_i == 1'b1))             value_o <= value_o-1;         else if ((a == 1'b0) && (a_i == 1'b0) && (b == 1'b1) && (b_i == 1'b0))             value_o <= value_o-1;          //change              else if ((a == 1'b1) && (a_i == 1'b1) && (b == 1'b1) && (b_i == 1'b0))                 value_o <= value_o-1;         else if ((a == 1'b0) && (a_i == 1'b1) && (b == 1'b1) && (b_i == 1'b1))                 value_o <= value_o-1;         else if ((a == 1'b0) && (a_i == 1'b0) && (b == 1'b0) && (b_i == 1'b1))                         value_o <= value_o-1;         else if ((a == 1'b1) && (a_i == 1'b0) && (b == 1'b0) && (b_i == 1'b0))                                 value_o <= value_o-1; // after           else if (a == a_i ==b == b_i )             value_o <= value_o-1;             end       end   end    always@ (posedge clk) // kasneje potrebo vezat za up_down_o   begin              //steje dol       if (value_cmp > value_o)         up_down_o <= 0;        //steje gor       else if (value_cmp < value_o)           up_down_o <= 1;           end         endmodule

it can shortened replacing if-else chains case suggest. here dense implementation. in kind of problems can use tables (lut).

  always@ (posedge clk or posedge reset)   begin     <= a_i;     b <= b_i;     value_cmp <= value_o;       if (reset || r_i)     begin       value_o<= 8'b0;       value_cmp <=8'b0;       end      else if (enable_i)     begin  //up or down       if (up_down_i)       begin           case({a,a_i,b,b_i})             //up             4'b0001, 4'b0111,             4'b1110, 4'b1000,             // change             4'b0100, 4'b1101,             4'b1011, 4'b0010:                 value_o <= value_o+1;         endcase         if (a == a_i ==b == b_i )             value_o <= value_o+1;          end        else       begin          case({a,a_i,b,b_i})         //down          4'b0100, 4'b1101,         4'b1011, 4'b0010,         //change           4'b1110, 4'b0111,         4'b0001, 4'b1000:             value_o <= value_o-1;         endcase // after           else if (a == a_i ==b == b_i )             value_o <= value_o-1;             end       end   end

here reference lut implementations: https://www.csee.umbc.edu/~tinoosh/cmpe415/slides/rom-lut-verilog.pdf


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