io - how to read image file and convert it to bits in vhdl -

i trying read image file using textio package in vhdl. if open .jpg notepad , junk data ascii data . here trying read these ascii data , convert them bytes.

below code:

library ieee; use ieee.std_logic_1164.all; use std.textio.all; use ieee.std_logic_textio.all;  entity file_io   port (      clk:             in  std_logic;      data:            out std_logic_vector(7 downto 0)  );  end entity;   architecture behav of file_io  signal test_data : std_logic_vector(7 downto 0); use ieee.numeric_std.all;  use std.textio.all; use ieee.std_logic_textio.all; begin  file_reader:process(clk)     file f    : text open read_mode "c:\users\public\pictures\sample pictures\chrysanthemum.jpg";     variable l:   line;     variable var_int:   integer:= 0;     variable var_char:   character;    begin  if rising_edge(clk)         while not endfile(f) loop                  readline(f, l);          read(l, var_char);          var_int := character'pos(var_char);          test_data  <= std_logic_vector(to_unsigned(var_int, test_data'length));           end loop;      end if;     data <= test_data;   end process; end architecture behav; 

testbench:

library ieee; use ieee.std_logic_1164.all; use std.textio.all;  entity file_io_test  end file_io_test;  architecture behavior of file_io_test use work.io.all;     signal clk:         std_logic := '0';     signal data: std_logic_vector(7 downto 0);      -- clock period definitions     constant clk_period : time := 10 ns;      begin       -- instantiate unit under test (uut)     uut:      entity work.file_io(behav)     port map (            clk => clk,         data => data           );      -- clock process definitions( clock 50% duty cycle generated here.      clk_process :process        begin          clk <= '1';          wait clk_period/2;  --for 5 ns signal '1'.           clk <= '0';          wait clk_period/2;  --for next 5 ns signal '0'.       end process;     end behavior;   

i getting 1 byte in waveform. expected result : every clock cycle new character should rread , new byte should obtained.

below waveform:

below image trying read:

the question has fundamental flaw. can't use textio read binary values, it's text.

see ieee std 1076-2008 16.4 package textio paragraphs 3 (in part) , 4:

procedures readline, writeline, , tee declared in package textio read , write entire lines of file of type text. procedure readline causes next line read file , returns value of parameter l access value designates object representing line. if parameter l contains non-null access value @ start of call, procedure may deallocate object designated value. the representation of line not contain representation of end of line. ...

the language not define representation of end of line. implementation shall allow possible values of types character , string written file. however, implementation permitted use values of types character , string line delimiters, might not possible read these values text file.

and can demonstrated chrysanthemum.jpg:

it possible in vhdl read raw characters 1 @ time (matching need).

see ieee std 1076-2008 5.5 file types:

so have declare file type , these procedures defined implicitly.

we can use them invoke raw read, without end of line issues caused textio:

library ieee; use ieee.std_logic_1164.all;  entity file_io     port (         clk:    in  std_logic;         data:   out std_logic_vector(7 downto 0);         done:   out boolean  );  end entity;  architecture foo of file_io     use ieee.numeric_std.all; begin  file_reader:     process (clk)         -- "c:\users\public\pictures\sample pictures\chrysanthemum.jpg";         constant filename:  string := "chrysanthemum.jpg"; -- local sim         variable char_val:  character;         variable status: file_open_status;         variable openfile:  boolean;  -- false default         type f file of character;         file ffile: f;         variable char_count:    natural := 0;     begin         if rising_edge (clk)             if not openfile                 file_open (status, ffile, filename, read_mode);                 if status /= open_ok                     report "file_open_status = " &                              file_open_status'image(status)                     severity failure;                 end if;                 report "file_open_status = " & file_open_status'image(status);                 openfile := true;             else                  if not endfile(ffile)                     read(ffile, char_val);                     -- report "char_val = " & character'image(char_val);                     char_count := char_count + 1;                     data  <= std_logic_vector (                              to_unsigned(character'pos(char_val),                              data'length) );                  end if;                  if endfile(ffile)  -- can occur after last character                     report "endfile, read " &                            integer'image(char_count) & "characters";                     done <= true;                     file_close(ffile);                 end if;             end if;         end if;     end process; end architecture foo;  library ieee; use ieee.std_logic_1164.all;  entity file_io_test  end file_io_test;  architecture behavior of file_io_test     signal clk:         std_logic := '0';     signal data:        std_logic_vector(7 downto 0);     signal done:        boolean;     constant clk_period: time := 10 ns; begin uut:     entity work.file_io(foo)         port map (            clk => clk,            data => data,            done => done         );  clk_process:     process     begin         if not done              clk <= '1';              wait clk_period/2;               clk <= '0';              wait clk_period/2;          else              wait;          end if;      end process; end architecture behavior;   

now can have characters can delimit line show in our read:

note package std.textio not made visible through context item.